The etching rate of conductive material (e.g., polysilicon) over different p-diffusion and n-diffusion work metals is inherently different. When forming gate stacks this different etching rate results in over etching and exposure of the underlying metal for certain gate stacks and gate stacks that are notched and have flared profile. As semiconductor devices continue to be scaled to smaller dimensions even small amounts of notched or flared gate profiles will significantly hinder device performance.